1. Field of the Invention
The present invention relates to a clock circuit for supplying clock signals in synchronization with a plurality of circuits, more particularly to a clock circuit which is capable of minimizing an arrival time difference of synchronized clock signals among a plurality of circuits in a system such as a computer system.
2. Description of Related Art
In a system having a plurality of circuits such as a computer system, circuits constituting the system are driven by clock signals in synchronization with each other. These synchronized clock signals are ordinarily generated by a clock generator and supplied to each of the circuits.
In the computer system, with the advance of operation speeds of microprocessors (CPU) circuits, such as a memory, have been able to operate at high speed. Furthermore, the development of functions of the system increases the number of circuits which constitute the system. Under such circumstances, a clock generator which can generate plural frequencies and supply the same frequency to a plurality of circuits has been put into practice.
FIG. 1 is a block diagram showing an example of a computer system which uses a conventional clock generator. In the system shown in FIG. 1, clock signals generated by the clock generator 1 are supplied to the four circuits including the CPU 2, the memory controller 3, the base SDRAM 4 used as an already incorporated memory, and the optional SDRAM 5 used as an additionally incorporated memory, which constitute the system.
In such a system, since the distances between the clock generator and each circuit are different, delay times of the clock signals are made to be different from each other among the circuits due to wiring impedance. As a result, a so called xe2x80x9cskewxe2x80x9d occurs in which the arrival times of the clock signal to each of the circuits are different from each other. More specifically, as a speed of the clock signals becomes higher, the cloak skew becomes more significant. In order to avoid this problem, the system of FIG. 1 is designed such that the arrival times of the clock signals are equal among the circuits by providing the dummy wiring 6 to adjust the lengths of the wiring from the clock generator to the circuits.
However, when the dummy wiring 6 is employed, the system of FIG. 1 gives rise to two problems. First, there is a need for an excessive space on the board to form the dummy wiring. Second, the dummy wiring causes the occurrence of EMI and crosstalk noises.
An object of the present invention is to provide a circuit for supplying clock signals and minimizing the difference among arrival times of the clock signals to a plurality of circuits.
Another object of the present invention is to reduce the amount of wiring in the circuit board in which a plurality of circuits are formed, thereby reducing the occurrence of EMI and crosstalk noises.
Still another object of the present invention is to provide a method for supplying clock signals which are capable of minimizing the difference among arrival times of the clock signals to a plurality of circuits.
Moreover, still another object of the present invention is to provide a computer system which is capable of minimizing the difference among arrival times of clock signals to a plurality of circuits and reducing the occurrence of EMI and crosstalk noises.
The present invention is directed to a clock circuit which supplies clock signals synchronized with each other to a plurality of circuits. The clock circuit includes a clock generator and a driver for outputting each of the clock signals supplied from the clock generator. Each signal being output with a delay from other signals to corresponding one of the plurality of circuits so that a difference of arrival times of clock signals is minimized among the plurality of circuits.
Another embodiment of the present invention is directed to a computer system which includes a CPU, a memory controller, a memory and a clock circuit for supplying clock signals in synchronization with each other. The clock circuit outputs the clock signals by delaying them for each of the plurality of circuits so that a difference among arrival times of the clock signals to the plurality of circuits is minimized.
Another embodiment of the present invention is directed to a method for supplying clock signals synchronized with each other to a plurality of circuits. The method includes the steps of setting delay times of the clock signals for corresponding one of the circuits and outputting the clock signals with a delay time predetermined for each circuit so that a difference among the arrival times of the clock signals to a plurality of circuits is minimized.